1. Field of the Invention
The present invention relates to an electrical package and manufacturing method thereof. More particularly, the present invention relates to an electrical package having a support substrate fabricated from a conductive material and manufacturing method thereof.
2. Description of the Related Art
Flip chip interconnect technology is a packaging technique for connecting a die to a carrier electrically. To form a flip chip package, an array of die pads is formed on the active surface of a die and then bumps are attached to the respective die pads. Thereafter, the die is flipped over such that the bumps are aligned and bonded to the bump pads on the surface of a carrier. Furthermore, the carrier has internal circuits for connecting with an external electronic device. Hence, the die can be electrically connected to the external device through the bumps and internal circuits inside the carrier. Since the flip chip technology can produce a high pin count chip package with a smaller package size and a shorter signal path length, it has been widely adopted in the semiconductor manufacturing industry. The most common types of chip packages that can be produced using the flip chip technology include the flip-chip/ball grid array (FC/BGA) and the flip-chip/pin grid array (FC/PGA), for example.
FIG. 1 is a schematic cross-sectional view of a conventional flip chip ball grid array electrical package. The electrical package 100 in FIG. 1 comprises a substrate 110, a plurality of bumps 120, a die 130 and a plurality of solder balls 140. The substrate 110 has a top surface 112 and a bottom surface 114. Furthermore, the substrate 110 has a plurality of bump pads 116a and a plurality of ball pads 116b thereon. The die 130 has an active surface 132 and a backside 134. The active surface 132 of the die 130 refers to the surface with the most active devices (not shown). The die 130 also has a plurality of die pads 136 on the active surface 132 serving as a medium for outputting signals from the die 130. The bump pads 116a on the substrate 110 are distributed to correspond with the position of the die pads 136. Each bump 120 is electrically and structurally connected to one of the die pads 136 on the die 130 and a corresponding bump pad 116a on the substrate 110. The solder balls 140 are attached to various solder pads 116b for connecting to an external electrical device both electrically and structurally.
In the conventional process, the circuits inside the substrate 110 and contact points 116a, 116b on the exposed surface of the substrate are formed before assembling the die 130 to the substrate 110. Thereafter, an underfill layer 150 is dispensed into the space between the top surface 112 of the substrate 110 and the active surface 132 of the die 130. The underfill layer 150 not only protects the bump pads 116a, the die pads 136 and the bumps 120, but also buffers any stress between the substrate 110 and the die 130 due to a mismatch in thermal expansion coefficients. In brief, the die pads 136 on the die 130 and the bump pads 116a on the substrate 110 are both electrically and structurally connected through the bumps 120. The bump pads 116a and the solder ball pads 116b on the bottom surface 114 are electrically connected via the internal circuits within the substrate 110. Finally, the solder ball pads 116b and an external device are connected electrically and structurally via the solder balls 140.
To produce high-density circuits within the substrate, a build-up method is often deployed to form a circuit layer on the surfaces of a dielectric core and then using a plated through hole (PTH) to connect the two circuit layers electrically. However, because a substrate having a thin dielectric core is vulnerable to warping by heat, the dielectric core must have a sufficient thickness to provide structural stiffness for withstanding warping stress. This renders any further reduction of the thickness of the dielectric core difficult.
Conventionally, a plated through hole is formed by laser-drilling the dielectric core form a fine hole. Thereafter, an electroplating operation is performed to coat a metallic layer over the interior wall of the hole so that the circuit layers on each side of the dielectric core are electrically connected. However, drilling with a laser is quite an expensive operation, thereby increasing the cost of fabricating the substrate. Moreover, the conventional fabrication method can no longer reduce the diameter of the plated through hole any further. In other words, the conventional method of forming plated through holes in a dielectric core has become a bottleneck for increasing the circuit density within the substrate.